ISP1362 VHDL interface for DE2
A standalone (NIOS II free) interface in VHDL to the ISP1362 USB device for Altera DE2 Development board.
Project maintained by mzakharo
Hosted on GitHub Pages — Theme by mattgraham
The interface is designed to enable simple, fast, and reliable communication with DE2 board and replace UART interfaces and NIOS II based designs typically used for this task.
Design is written using techniques from Gaisler Method for writing VHDL
Features:
- Fmax: 420MHz - limit due to max I/O toggle rate.
- Area: 352 LEs.
- 2 Bulk endpoints (IN/OUT)
- Test host software application for Windows using libusb-win32
Limitations:
- Transfer rate: 180 KB/s with 2 Bytes/USB Transaction. ISP1362 supports up to 1MB/s with up to 64 Bytes/USB Transaction.
- Hardware flow control: ISP1362 can detect overflow of internal buffers. Currently overflows must be avoided by the host software application.